2025年R型指令以上

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宏定义文件

define RstEnable 1’b1 define RstDisable 1’b0 define RomEnable 1b1 define RomDisable 1’b0 define Zero 0
define Valid 1’b1
define Invalid 1’b0
/／指令外部编码
// I 型编码
define Inst _ ori 6’b001101
define Inst _ andi 6’b001100
define Inst _ xori 6’b001110
define Inst _ addi 6’b001000
define Inst _ subi 6’b001001
define Inst _lui6’b001111
// R 型编码
define Inst _ reg 6’b000000
define Inst _ add 6’b
define Inst _ sub 6’b
define Inst _ and 6’b
define Inst _ or 6’b
define Inst _ xor 6’b
define Inst _ sll 6’b000000
define Inst _ srl 6’b000010
define Inst _ sra 6’b000011
/／内部供 EX 的编码
define Nop 6’b000000
define Or6’b000001
define And 6’b000010
define Xor 6’b000011
define Add 6’b000100
define Sub 6’b000101
define Lui 6’b/／此处重新修改了 define Sll 6’b000110
define Srl 6’b000111
define Sra 6’b001000

InstMem
include "define.v"; //6、指令存储器 module InstMem( input wire ce, input wire [31:0] addr, output reg [31:0] data ); reg [31:0] instmem [1023 : 0]; always@(*) if(ce ==RomDisable)
data = `Zero;
else
data = instmem[addr[11 : 2]];
initial
begin
//ori R0,1100 – R1 --00001100
instmem [0] = 32’h;
//ori R0,0020 – R2 --00000020
instmem [1] = 32’h;
//ori R0,ff00 – R3 --0000ff00
instmem [2] = 32’h3403ff00;
//ori R0,ffff – R4 --0000ffff
instmem [3] = 32’h3404ffff;
//andi R0,ffff --R5 --00000000
// instmem [4] = 32’h3005ffff;
//xori R0,ffff --R6 --0000ffff
// instmem [5] = 32’h3806ffff;
//addi R0,ffff --R7 --ffffffff
// instmem [6] = 32’h2007ffff;
//subi R0,ffff --R8 --00000001
// instmem [7] = 32’h2408ffff;
//lui R0,ffff --R9 --ffff0000
// instmem [8] = 32’h3C09ffff;

 //R1=00001100 R2=00000020 instmem [4] = 32'b000000_00001_00010_00101_00000_;//add,R5,R1,R2 00001120 instmem [5] = 32'b000000_00001_00010_00110_00000_;//or,R6,R1,R2 00001120 instmem [6] = 32'b000000_00001_00010_00111_00000_;//sub,R7,R1,R2 000010e0 instmem [7] = 32'b000000_00001_00010_01000_00000_;//and,R8,R1,R2 00000000 instmem [8] = 32'b000000_00001_00010_01001_00000_;//xor,R9,R1,R2 00001120 //lui R0,ffff --R10 --ffff0000 instmem [9] = 32'h3C0Affff; //R11=fffe0000 R12=7fff8000 R13=ffff8000 // Ra=sa={25'b0,imm[10:6]} instmem [10] = 32'b000000_00000_01010_01011_00001_000000;//sll,R11,Ra,R10 instmem [11] = 32'b000000_00000_01010_01100_00001_000010;//srl,R12,Ra,R10 instmem [12] = 32'b000000_00000_01010_01101_00001_000011;//sra,R13,Ra,R10 end

讯享网

endmodule

ID
`include “define.v”;
//2、为操作数做准备
//把指令32的i型指令inst
//6op 5rega 5regc 16imm
//regaData regbData
module ID (
input wire rst,
input wire [31:0] inst,
input wire [31:0] regaData_i,
input wire [31:0] regbData_i,
output reg [5:0] op,
output reg [31:0] regaData,
output reg [31:0] regbData,
output reg regaRead,
output reg regbRead,
output reg regcWrite,
output reg [4:0] regaAddr,
output reg [4:0] regbAddr,
output reg [4:0] regcAddr
);
//操作指令
wire [5:0] inst_op = inst[31:26];
//扩展的立即数
reg [31:0] imm;
//用于R型指令
wire[5:0] func = inst[5:0];
//用于R型移位指令给regaAddr赋值
wire[5:0] shamt= inst[10:6];
//用于R型移位指令给regaData赋值
wire[31:0] sa= {27’h0,inst[10:6]};

讯享网//用于R型移位指令 always@(*) if(rst == `RstEnable) begin op = `Nop; regaRead = `Invalid; regbRead = `Invalid; regcWrite = `Invalid; regaAddr = `Zero; regbAddr = `Zero; regcAddr = `Zero; imm = `Zero; end else case(inst_op) `Inst_ori: begin op = `Or; regaRead = `Valid; regbRead = `Invalid; regcWrite = `Valid; regaAddr = inst[25:21]; regbAddr = `Zero; regcAddr = inst[20:16]; imm = {16'h0, inst[15:0]}; end `Inst_andi: begin op = `And; regaRead = `Valid; regbRead = `Invalid; regcWrite = `Valid; regaAddr = inst[25:21]; regbAddr = `Zero; regcAddr = inst[20:16]; imm = {16'h0, inst[15:0]}; end `Inst_xori: begin op = `Xor; regaRead = `Valid; regbRead = `Invalid; regcWrite = `Valid; regaAddr = inst[25:21]; regbAddr = `Zero; regcAddr = inst[20:16]; imm = {16'h0, inst[15:0]}; end `Inst_addi: begin op = `Add; regaRead = `Valid; regbRead = `Invalid; regcWrite = `Valid; regaAddr = inst[25:21]; regbAddr = `Zero; regcAddr = inst[20:16]; imm = { 
  
    
  {16{inst[15]}}, inst[15:0]}; end `Inst_subi: begin op = `Sub; regaRead = `Valid; regbRead = `Invalid; regcWrite = `Valid; regaAddr = inst[25:21]; regbAddr = `Zero; regcAddr = inst[20:16]; imm = { 
  
    
  {16{inst[15]}}, inst[15:0]}; end `Inst_lui: begin op = `Lui; regaRead = `Valid; regbRead = `Invalid; regcWrite = `Valid; regaAddr = inst[25:21]; regbAddr = `Zero; regcAddr = inst[20:16]; imm = {inst[15:0],16'h0}; end `Inst_reg: case(func) `Inst_add: begin op = `Add; regaRead = `Valid; regbRead = `Valid; regcWrite = `Valid; regaAddr = inst[25:21]; regbAddr = inst[20:16]; regcAddr = inst[15:11]; imm = `Zero; end `Inst_or: begin op = `Or; regaRead = `Valid; regbRead = `Valid; regcWrite = `Valid; regaAddr = inst[25:21]; regbAddr = inst[20:16]; regcAddr = inst[15:11]; imm = `Zero; end `Inst_sub: begin op = `Sub; regaRead = `Valid; regbRead = `Valid; regcWrite = `Valid; regaAddr = inst[25:21]; regbAddr = inst[20:16]; regcAddr = inst[15:11]; imm = `Zero; end `Inst_and: begin op = `And; regaRead = `Valid; regbRead = `Valid; regcWrite = `Valid; regaAddr = inst[25:21]; regbAddr = inst[20:16]; regcAddr = inst[15:11]; imm = `Zero; end `Inst_xor: begin op = `Xor; regaRead = `Valid; regbRead = `Valid; regcWrite = `Valid; regaAddr = inst[25:21]; regbAddr = inst[20:16]; regcAddr = inst[15:11]; imm = `Zero; end //修改了下面的组合逻辑两个always语句 `Inst_sll: begin op = `Sll; regaRead = `Invalid; regbRead = `Valid; regcWrite = `Valid; regaAddr = shamt;//regaRead 无效，但regaAddr不为`Zero regbAddr = inst[20:16]; regcAddr = inst[15:11]; imm = `Zero; end `Inst_srl: begin op = `Srl; regaRead = `Invalid; regbRead = `Valid; regcWrite = `Valid; regaAddr = shamt; regbAddr = inst[20:16]; regcAddr = inst[15:11]; imm = `Zero; end `Inst_sra: begin op = `Sra; regaRead = `Invalid; regbRead = `Valid; regcWrite = `Valid; regaAddr = shamt;//无效，但不为`Zero regbAddr = inst[20:16]; regcAddr = inst[15:11]; imm = `Zero; end default: begin regaRead = `Invalid; regbRead = `Invalid; regcWrite = `Invalid; regaAddr = `Zero; regbAddr = `Zero; regcAddr = `Zero; imm = `Zero; end endcase default: begin op = `Nop; regaRead = `Invalid; regbRead = `Invalid; regcWrite = `Invalid; regaAddr = `Zero; regbAddr = `Zero; regcAddr = `Zero; imm = `Zero; end endcase

讯享网

always@(*) if(rst == `RstEnable) regaData = `Zero; else if(regaRead == `Valid) regaData = regaData_i; else regaData = imm;

//二选一 regbData= regbData_i : imm
always@(*)
if(rst == RstEnable) regbData =Zero;
else if(regbRead == `Valid)
regbData = regbData_i;
else
regbData = imm;
*/

讯享网//三选一 regaData= regaData_i : imm ：sa always@(*) if(rst == `RstEnable) regaData = `Zero; else if(regaRead == `Valid) regaData = regaData_i; else if(regaRead == `Invalid && regaAddr==`Zero) regaData = imm; else regaData = sa;

//三选一 regbData= regbData_i : imm ：sa
always@(*)
if(rst == RstEnable) regbData =Zero;
else if(regbRead == Valid) regbData = regbData_i; else if(regbRead ==Invalid && regbAddr==`Zero)
regbData = imm;
else
regbData = sa;
endmodule

include "define.v"; //3、执行指令模块 module EX ( input wire rst, input wire [5:0] op, input wire [31:0] regaData, input wire [31:0] regbData, input wire regcWrite_i, input wire [4:0] regcAddr_i, output reg [31:0] regcData, output wire regcWrite, output wire [4:0] regcAddr ); always@(*) if(rst ==RstEnable)
regcData = Zero; else case(op)Or:
regcData = regaData | regbData;
And: regcData = regaData & regbData;Xor:
regcData = regaData ^ regbData;
Add: regcData = regaData + regbData;Sub:
regcData = regaData - regbData;
`Lui:
regcData = regaData | regbData;

 `Sll: regcData = regbData << regaData; `Srl: regcData = regbData >> regaData; `Sra: regcData = ($signed(regbData)) >>> regaData; default: regcData = `Zero; endcase assign regcWrite = regcWrite_i; assign regcAddr = regcAddr_i;

endmodule

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