一、VGA原理

参见文章VGA（一）

二、移动方块原理

2.1 方块的初始位置和大小

初始位置设置为（H0，V0），它距离有效显示区域原点的水平距离为Q_HS_RANGE=20，垂直距离为Q_VS_RANGE=15。方块的大小可以自行设定，定义常量Q_LONG和Q_WIDTH

2.2 方块的显示

根据水平和垂直方向计数器，产生2个方向的使能脉冲，进而产生方块有效显示区域的使能脉冲en0。

2.3 方块的移动

方块每1s移动一次。这个用计数器来实现，计数到1s时产生一个脉冲，方块根据脉冲移动，移动的距离可以自行调整，注意不能移动到边界之外，所以移动坐标（h0，v0）有一个最大值限制。

讯享网

三 、代码

顶层代码如下：

module vga_quadrate (

input wire clk, input wire rst_n, output wire [7:0] vga_rgb, output wire vga_hs, output wire vga_vs 

);

讯享网wire clk_25m; wire pll_locked; pll pll_inst ( .areset ( ~rst_n ), .inclk0 ( clk ), .c0 ( clk_25m ), .locked ( pll_locked) ); vga_ctrl vga_ctrl_inst ( .clk (clk_25m ), .rst_n (pll_locked ), .vga_rgb (vga_rgb ), .vga_hs (vga_hs ), .vga_vs (vga_vs ) ); 

endmodule

2、vga_ctrl模块

`define VGA_640x480x60 // choose different video standard,revise PLL clk ,alter cnt WIDTH //`define VGA_640X480X75 //`define VGA_800X600X60 //`define VGA_800X600X75 //`define VGA_1024X768X60 //`define VGA_1024X768X75 //`define VGA_1280X1024X60 //`define VGA_1280X800X60 //`define VGA_1440X900X60 module vga_ctrl ( input wire clk, input wire rst_n, output reg [7:0] vga_rgb, output reg vga_hs, output reg vga_vs ); //================ VGA_640X480X60 ========================================================= `ifdef VGA_640x480x60 // PLL clk = 25M = 640x480x60 localparam HS_A = 96; // synchronous pulse, horizontal localparam HS_B = 48; // back porch pulse localparam HS_C = 640; // display interval localparam HS_D = 16; // Front porch localparam HS_E = 800; // horizontal cycles localparam VS_A = 2; // synchronous pulse, vertical localparam VS_B = 33; localparam VS_C = 480; localparam VS_D = 10; localparam VS_E = 525; localparam HS_WIDTH = 10; localparam VS_WIDTH = 10; `endif //================ VGA_800X600X60 ========================================================= // //`ifdef VGA_800X600X60 // PLL clk = 40.0M // // localparam HS_A = 128; // localparam HS_B = 88; // localparam HS_C = 800; // localparam HS_D = 40; // localparam HS_E = 1056; // // localparam VS_A = 4; // localparam VS_B = 23; // localparam VS_C = 600; // localparam VS_D = 1; // localparam VS_E = 628; // // localparam HS_WIDTH = 11; // different resolution correspond to different couter width // localparam VS_WIDTH = 10; // //`endif //===================================================================================================== parameter Q_HS_RANGE = 20; // horizontal range of original display point to H0 parameter Q_VS_RANGE = 15; parameter Q_LONG = 40; parameter Q_WIDTH = 30; parameter H0 = HS_A + HS_B + Q_HS_RANGE - 1; parameter V0 = VS_A + VS_B + Q_VS_RANGE - 1; parameter T_1s = 50_000_000; reg [25:0] cnt_1s; // 1s counter reg [HS_WIDTH - 1:0] h0; // quadrate_hs move point reg [VS_WIDTH - 1:0] v0; // quadrate_vs move point reg [HS_WIDTH - 1:0] cnt_hs; // counter for vertical synchronous signal reg [VS_WIDTH - 1:0] cnt_vs; // counter for horizontal synchrous signal wire en_hs; // dsiplay horizontal enable wire en_vs; // display vertical enable wire en; // effective display zone wire flag; // T_1s flag wire en_hs0; wire en_vs0; wire en0; // quadrate display enable always @ (posedge clk, negedge rst_n) if (!rst_n) cnt_1s <= 0; else if (cnt_1s < T_1s - 1) cnt_1s <= cnt_1s + 1'b1; else cnt_1s <= 0; assign flag = (cnt_1s == T_1s - 1) ? 1'b1 : 1'b0; always @ (posedge clk, negedge rst_n) if (!rst_n) h0 <= H0; else if (flag) if (h0 < HS_E - HS_D - 2 * Q_LONG) h0 <= h0 + 10'd80; else h0 <= H0; else h0 <= h0; always @ (posedge clk, negedge rst_n) if (!rst_n) v0 <= V0; else if (flag) if (v0 < VS_E - VS_D - 2 * Q_WIDTH) v0 <= v0 + 10'd60; else v0 <= V0; else v0 <= v0; always @ (posedge clk, negedge rst_n) if (!rst_n) cnt_hs <= 0; else if (cnt_hs < HS_E - 1) cnt_hs <= cnt_hs + 1'b1; else cnt_hs <= 0; always @ (posedge clk, negedge rst_n) if (!rst_n) cnt_vs <= 0; else if (cnt_hs == HS_E - 1) if (cnt_vs < VS_E - 1) cnt_vs <= cnt_vs + 1'b1; else cnt_vs <= 0; else cnt_vs <= cnt_vs; always @ (posedge clk, negedge rst_n) if (!rst_n) vga_hs <= 1'b1; else if (cnt_hs < HS_A - 1) vga_hs <= 1'b0; else vga_hs <= 1'b1; always @ (posedge clk, negedge rst_n) if (!rst_n) vga_vs <= 1'b1; else if (cnt_vs < VS_A - 1) vga_vs <= 1'b0; else vga_vs <= 1'b1; assign en_hs = (cnt_hs > HS_A + HS_B - 1) && (cnt_hs < HS_E - HS_D); assign en_vs = (cnt_vs > VS_A + VS_B - 1) && (cnt_vs < VS_E - VS_D); assign en = en_hs && en_vs; assign en_hs0 = (cnt_hs > h0 - 1) && (cnt_hs < h0 + Q_LONG); assign en_vs0 = (cnt_vs > v0 - 1) && (cnt_vs < v0 + Q_WIDTH); assign en0 = en_hs0 && en_vs0; always @ (posedge clk, negedge rst_n) if (!rst_n) vga_rgb <= 8'b000_000_00; else if (en) if (en0) vga_rgb <= 8'b111_000_00; // red else vga_rgb <= 8'b000_111_00; // green else vga_rgb <= 8'b000_000_00; endmodule 

四、下板验证